Virtually every computer system requires some sort of memory. Data and computer programs for instructing the computer as to how the data is to be processed, are stored in a computer's memory. At a top level, magnetic and optical storage devices (e.g., hard disk drives, floppy disk drives, tape drives, optical disk drives, etc.), are often used to store data and computer programs. These devices have high capacities and offer a relatively inexpensive medium for storing vast amounts of data. The data is retained, even when the devices are powered down. However, a major disadvantage with using these storage devices is their slow access times. These devices are electro-mechanical in nature and involve physically moving a transducer to the appropriate locations before data can be written or retrieved.
In order to gain faster access to the data, computers typically also contain on-board memory chips. These memory chips allow data to be accessed electronically. There are basically two types of memory chips: Read-Only Memory (ROM) and Random-Access Memory (RAM). ROM chips are used to store data of a permanent nature. The data is typically loaded into the ROM by the manufacturer. Once written, the data is retained by the ROM indefinitely, even when power is turned off. A user may not subsequently change or alter the data. RAM chips, on the other hand, are more flexible and versatile. Although RAM loses its data whenever power is removed, data can be repeatedly written to and read from the RAM any number of times. Although the term "random access memory" implies that the memory locations may be accessed in any desired sequence, it is common usage to denote any read/write memory as RAM. ("New IEEE Standard Dictionary of Electrical and Electronic Terms", 1993, p. 1064). In the context of this disclosure, "RAM" does not necessarily denote randomly accessible.
RAM chips can be subdivided into two categories: Static and Dynamic RAMs (SRAMs and DRAMs). SRAMs are generally constructed from latches, which endow the SRAMs with superior speed. However, SRAMs are relatively expensive to fabricate. Although DRAMs are slower, they are less expensive. Hence, many computer systems contain a large "main" memory consisting of DRAMs for storing the bulk of the data and a small "cache" of SRAM memory for storing copies of the most recently accessed data.
DRAMs are constructed from an array of extremely tiny capacitors, each of which can be charged and discharged, thereby allowing bits of data (i.e., charged="1" and discharged="0") to be digitally stored. Associated transistors are used to control these capacitors so that data can be written to and read from certain, specified locations or "addresses." Various DRAM structures are described in Weste & Eshraghian "Principles of CMOS VLSI Design" 1985, pp. 353-354 and Glasser & Dobberpuhl, and "Design and Analysis of VLSI Circuits", 1985, pp. 393-395.
FIG. 1 shows a portion of a prior art DRAM circuit. A 2.times.4 block comprising eight memory cells 101-108 is shown, wherein each memory cell includes three transistors and a capacitor. An individual memory cell has the capability of storing one bit of data. The bit of data is stored on the capacitor 114 which is sized to ensure adequate data storage time. Capacitor 114 may consist solely of the parasitic gate capacitance of transistor 113 and/or the parasitic drain capacitance of transistor 111, or it may include additional capacitance. Horizontal data lines DATA0-DATA3 route data to/from the rows of memory cells. In addition, each column of memory cells has a READ line as well as a WRITE line. These READ and WRITE lines are used for determining whether data is to be written to or read from a particular memory cell.
For example, memory cell 101 is comprised of a write transistor 111, a read transistor 112, a storage transistor 113, and capacitor 114. A write operation to memory cell 101 proceeds by placing data (either +5 V="1" or 0 V="0") on the DATA0 line and asserting the WRITE line 109. A read operation proceeds by precharging the DATA0 line and asserting the READ line 110, thereby turning on the read transistor 112 and opening a current path to the storage transistor 113. If capacitor 114 is charged, the storage transistor 113 is turned on, thereby causing the precharged DATA0 line to be pulled down to ground (0 V). Conversely, if capacitor 114 is not charged, the storage transistor 113 is turned off and the DATA0 line remains charged (+5 V). Because the data retrieved is backwards, a data inversion is subsequently required to return the correct data. It should be noted that the data stored in adjacent cells remain unaffected due to the high impedance of their respective write transistors and read transistors.
This prior art DRAM memory cell design is replicated millions of times. Computer systems today often come with 8, 16, or even 32 megabytes of DRAM. Hence, any improvement to this standard DRAM design would be magnified a million fold. The present invention offers such an improvement. The DRAM design of the present invention significantly reduces fabrication costs while, at the same time, maximizes storage capacity.